The ever growing demand for greater functionality and better performance from integrated circuits and systems have been addressed in part by shrinking the size of transistors and interconnections. While the switching speed of transistors has improved remarkably, signal propagation speed along metal interconnects has not, because the fundamental RC time constant does not scale down with dimensional scaling. This is aggravated at very high frequencies (>10 GHz) where the parasitic inductive/capacitive effect and skin effects cannot be ignored. Even with the implementation of complex System-on-Chip (SoC) and Systems-in-Package (SiP) to provide enhanced functionality, metal interconnect (even with Cu) delays remain a major road block to enhancing speed performance.
Two technological developments have helped to improve, to some extent, speed performance: (i) low-k dielectrics to reduce the capacitance between tracks/substrate, and (ii) three dimensional integration with through silicon vias (TSV), where silicon chips (or dies) are stacked and bonded one on top of the other and electrically connected vertically by metal (Cu) through these TSVs. In spite of these technological advancements, industry recognises that scaling deteriorates the performance of interconnects and that deterioration has already become a significant limiter in overall circuit performance. ITRS2008 (International Road Map for Semiconductors) reports that as additional layers of silicon chips are stacked, the RC time constant improvement from three-dimensional integration flattens out. The problem is further exacerbated as technology and industry moves below the 45 nm node.
Conventional systems have the following characteristics: (a) connectivity between various levels of a 3D die stack only uses metal interconnect in through silicon vias (TSVs); (b) silicon photonics are only focused at the silicon die level; and (c) PCB optical connectivity uses polymer waveguides.